The present invention relates to the field of integrated circuits and in particular, to providing a flexible dual port memory within an integrated circuit. Programmable integrated circuits, such as programmable logic devices (PLD), are becoming more complex and continually evolving to provide more usable programmable features in a single integrated circuit. Modern programmable logic devices incorporate programmable logic including logic gates, and look-up tables, as well as embedded user programmable memory or configuration random access memory (CRAM).
Despite the success of programmable logic, there is a continuing desire to provide greater functionality in a programmable logic device, and at the same time, to provide greater flexibility. There is also a need to provide higher performance user memories also. Currently, the memories for a programmable logic device are typically pre-defined in size and these pre-defined memories are used under restrictions. Thus, the restrictions limit the flexibility of using the memories, e.g., when a portion of the programmable logic device that contains the memory or combinational logic that includes memory is unused, the memory remains unused.
Accordingly, there is a need for a highly flexible memory, which may be selectively configured between combinational logic functions and memory functions within a programmable logic device.